A New Approach to a FSM Implementation in Embedded Memory Blocks of FPGA Devices with Use of the Functional Decomposition

Since modern FPLD devices have very complex structure there is necessity to develop new methods that would allow fully exploiting the possibilities these devices offer. The paper presents a general method for the synthesis targeted to ROM-based implementation of sequential circuits using embedded memory blocks of programmable devices. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. This new approach allows reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.